EEE/CSE 120 : Digital Design Fundamentals
General Information:
Instructor: Professor Bahman Moraffah
Office: GWC 333
Office Hours: TTh 1:30-2:30 pm or by appointment
Course Link: Piazza
Email: bahman.moraffah@asu.edu
Course Objectives:
At the completion of this course, students will be able to:
Design, build, debug, and demonstrate the operation of arbitrarily complex synchronous ma- chines given a reasonable problem statement.
Set criteria to determine the “best” design and select the best design from the created designs.
Describe the operation of an elementary microprocessor.
Create an instruction set for an elementary microprocessor, and enter the instruction set into
the processor’s instruction PROM.
Enter a program in the processor's memory and execute the program.
Syllabus:
You can find the syllabus here
Laboratory:
Laboratory Manuals available on Canvas, Intel Quartus Prime Lite software available in the GWC 273 lab or online. Terasic DE10-Lite FPGA boards are available in the GWC 273 lab. Each student must submit an individual report.
Information regarding the labs is provided on Canvas.
You can find the schedule here.
Reference:
(Main Textbook) Introduction to Logic Design, 3rd Edition, by Alan B. Marcovitz, McGraw-Hill, 2010.
Contemporary Logic Design 2nd Edition by Randy H. Katz and Gaetano Borriello, 2004
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